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-rw-r--r--driver/e1000.c427
-rw-r--r--driver/e1000.h5
-rw-r--r--driver/keyboard.c9
-rw-r--r--driver/pci.c40
-rw-r--r--driver/pci.h1
5 files changed, 467 insertions, 15 deletions
diff --git a/driver/e1000.c b/driver/e1000.c
index 99194be..21d3924 100644
--- a/driver/e1000.c
+++ b/driver/e1000.c
@@ -1,4 +1,429 @@
+//https://github.com/blanham/ChickenOS/blob/master/src/device/net/e1000.c
+//https://wiki.osdev.org/Intel_Ethernet_i217
+#include <stdint.h>
+#include "log.h"
+#include "e1000.h"
+#include "kmalloc.h"
-void init_e1000()
+#define INTEL_VEND 0x8086 // Vendor ID for Intel
+#define E1000_DEV 0x100E // Device ID for the e1000 Qemu, Bochs, and VirtualBox emmulated NICs
+#define E1000_I217 0x153A // Device ID for Intel I217
+#define E1000_82577LM 0x10EA // Device ID for Intel 82577LM
+
+
+// I have gathered those from different Hobby online operating systems instead of getting them one by one from the manual
+
+#define REG_CTRL 0x0000
+#define REG_STATUS 0x0008
+#define REG_EEPROM 0x0014
+#define REG_CTRL_EXT 0x0018
+#define REG_IMASK 0x00D0
+#define REG_RCTRL 0x0100
+#define REG_RXDESCLO 0x2800
+#define REG_RXDESCHI 0x2804
+#define REG_RXDESCLEN 0x2808
+#define REG_RXDESCHEAD 0x2810
+#define REG_RXDESCTAIL 0x2818
+
+#define REG_TCTRL 0x0400
+#define REG_TXDESCLO 0x3800
+#define REG_TXDESCHI 0x3804
+#define REG_TXDESCLEN 0x3808
+#define REG_TXDESCHEAD 0x3810
+#define REG_TXDESCTAIL 0x3818
+
+
+#define REG_RDTR 0x2820 // RX Delay Timer Register
+#define REG_RXDCTL 0x3828 // RX Descriptor Control
+#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
+#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
+
+
+
+#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
+#define ECTRL_SLU 0x40 //set link up
+
+
+#define RCTL_EN (1 << 1) // Receiver Enable
+#define RCTL_SBP (1 << 2) // Store Bad Packets
+#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
+#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
+#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
+#define RCTL_LBM_NONE (0 << 6) // No Loopback
+#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
+#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
+#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
+#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
+#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
+#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
+#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
+#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
+#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
+#define RCTL_VFE (1 << 18) // VLAN Filter Enable
+#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
+#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
+#define RCTL_DPF (1 << 22) // Discard Pause Frames
+#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
+#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
+
+// Buffer Sizes
+#define RCTL_BSIZE_256 (3 << 16)
+#define RCTL_BSIZE_512 (2 << 16)
+#define RCTL_BSIZE_1024 (1 << 16)
+#define RCTL_BSIZE_2048 (0 << 16)
+#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
+#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
+#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
+
+
+// Transmit Command
+
+#define CMD_EOP (1 << 0) // End of Packet
+#define CMD_IFCS (1 << 1) // Insert FCS
+#define CMD_IC (1 << 2) // Insert Checksum
+#define CMD_RS (1 << 3) // Report Status
+#define CMD_RPS (1 << 4) // Report Packet Sent
+#define CMD_VLE (1 << 6) // VLAN Packet Enable
+#define CMD_IDE (1 << 7) // Interrupt Delay Enable
+
+
+// TCTL Register
+
+#define TCTL_EN (1 << 1) // Transmit Enable
+#define TCTL_PSP (1 << 3) // Pad Short Packets
+#define TCTL_CT_SHIFT 4 // Collision Threshold
+#define TCTL_COLD_SHIFT 12 // Collision Distance
+#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
+#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
+
+#define TSTA_DD (1 << 0) // Descriptor Done
+#define TSTA_EC (1 << 1) // Excess Collisions
+#define TSTA_LC (1 << 2) // Late Collision
+#define LSTA_TU (1 << 3) // Transmit Underrun
+
+// buffers
+#define E1000_NUM_RX_DESC 32
+#define E1000_NUM_TX_DESC 8
+
+struct e1000_rx_desc {
+ volatile uint64_t addr;
+ volatile uint16_t length;
+ volatile uint16_t checksum;
+ volatile uint8_t status;
+ volatile uint8_t errors;
+ volatile uint16_t special;
+} __attribute__((packed));
+
+struct e1000_tx_desc {
+ volatile uint64_t addr;
+ volatile uint16_t length;
+ volatile uint8_t cso;
+ volatile uint8_t cmd;
+ volatile uint8_t status;
+ volatile uint8_t css;
+ volatile uint16_t special;
+} __attribute__((packed));
+
+ uint8_t bar_type; // Type of BOR0
+ uint16_t io_base; // IO Base Address
+ uint32_t mem_base; // MMIO Base Address
+ bool eerprom_exists; // A flag indicating if eeprom exists
+ uint8_t mac [6]; // A buffer for storing the mack address
+ struct e1000_rx_desc *rx_descs[E1000_NUM_RX_DESC]; // Receive Descriptor Buffers
+ struct e1000_tx_desc *tx_descs[E1000_NUM_TX_DESC]; // Transmit Descriptor Buffers
+ uint16_t rx_cur; // Current Receive Descriptor Buffer
+ uint16_t tx_cur; // Current Transmit Descriptor Buffer
+
+
+
+
+void writeCommand( uint16_t p_address, uint32_t p_value)
+{
+// if ( bar_type == 0 )
+// {
+ (*((volatile uint32_t*)(mem_base+p_address)))=(p_value);
+// }
+// else
+// {
+ //outportl(io_base, p_address);
+ //outportl(io_base + 4, p_value);
+// }
+}
+
+uint32_t readCommand( uint16_t p_address)
+{
+// if ( bar_type == 0 )
+// {
+ return *((volatile uint32_t*)(mem_base+p_address));
+// }
+// else
+// {
+ //outportl(io_base, p_address);
+ //return inportl(io_base + 4);
+// }
+}
+
+bool detectEEProm()
+{
+ uint32_t val = 0;
+ writeCommand(REG_EEPROM, 0x1);
+
+ for(int i = 0; i < 1000 && ! eerprom_exists; i++)
+ {
+ val = readCommand( REG_EEPROM);
+ if(val & 0x10)
+ eerprom_exists = true;
+ else
+ eerprom_exists = false;
+ }
+
+ klog("eeprom %s",eerprom_exists?"YES":"NO");
+ return eerprom_exists;
+}
+
+uint32_t eepromRead( uint8_t addr)
+{
+ uint16_t data = 0;
+ uint32_t tmp = 0;
+ if ( eerprom_exists)
+ {
+ writeCommand( REG_EEPROM, (1) | ((uint32_t)(addr) << 8) );
+ while( !((tmp = readCommand(REG_EEPROM)) & (1 << 4)) );
+ }
+ else
+ {
+ writeCommand( REG_EEPROM, (1) | ((uint32_t)(addr) << 2) );
+ while( !((tmp = readCommand(REG_EEPROM)) & (1 << 1)) );
+ }
+ data = (uint16_t)((tmp >> 16) & 0xFFFF);
+ return data;
+}
+
+bool readMACAddress()
+{
+ if ( eerprom_exists)
+ {
+ uint32_t temp;
+ temp = eepromRead( 0);
+ mac[0] = temp &0xff;
+ mac[1] = temp >> 8;
+ temp = eepromRead( 1);
+ mac[2] = temp &0xff;
+ mac[3] = temp >> 8;
+ temp = eepromRead( 2);
+ mac[4] = temp &0xff;
+ mac[5] = temp >> 8;
+ }
+ else
+ {
+ uint8_t * mem_base_mac_8 = (uint8_t *) (mem_base+0x5400);
+ uint32_t * mem_base_mac_32 = (uint32_t *) (mem_base+0x5400);
+ if ( mem_base_mac_32[0] != 0 )
+ {
+ for(int i = 0; i < 6; i++)
+ {
+ mac[i] = mem_base_mac_8[i];
+ }
+ }
+ else return false;
+ }
+ return true;
+}
+
+
+void rxinit()
+{
+ uint8_t * ptr;
+ struct e1000_rx_desc *descs;
+
+ // Allocate buffer for receive descriptors. For simplicity, in my case khmalloc returns a virtual address that is identical to it physical mapped address.
+ // In your case you should handle virtual and physical addresses as the addresses passed to the NIC should be physical onesk
+
+ uint32_t alloc_pages=1+(sizeof(struct e1000_rx_desc)*E1000_NUM_RX_DESC + 16)/4096;
+
+ ptr = kballoc(alloc_pages);
+
+ descs = (struct e1000_rx_desc *)ptr;
+ for(int i = 0; i < E1000_NUM_RX_DESC; i++)
+ {
+ rx_descs[i] = (struct e1000_rx_desc *)((uint8_t *)descs + i*16);
+ rx_descs[i]->addr = kballoc(3); // what a waste :( TODO!
+ rx_descs[i]->status = 0;
+ }
+
+ /*
+ writeCommand(REG_TXDESCLO, (uint32_t)((uint64_t)ptr >> 32) );
+ writeCommand(REG_TXDESCHI, (uint32_t)((uint64_t)ptr & 0xFFFFFFFF));
+
+ writeCommand(REG_TXDESCLO, (uint32_t)(0) );
+ writeCommand(REG_TXDESCHI, (uint32_t)(ptr));
+ */
+
+ writeCommand(REG_RXDESCLO, ptr);
+ writeCommand(REG_RXDESCHI, 0);
+
+ writeCommand(REG_RXDESCLEN, E1000_NUM_RX_DESC * 16);
+
+ writeCommand(REG_RXDESCHEAD, 0);
+ writeCommand(REG_RXDESCTAIL, E1000_NUM_RX_DESC-1);
+ rx_cur = 0;
+
+ //enable receiving
+ uint32_t flags = (2 << 16) | (1 << 25) | (1 << 26) | (1 << 15) | (1 << 5) | (0 << 8) | (0 << 4) | (0 << 3) | ( 1 << 2);
+ writeCommand(REG_RCTRL, flags);
+ //writeCommand(REG_RCTRL, RCTL_EN| RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_2048);
+
+}
+
+void txinit()
+{
+ uint8_t * ptr;
+ struct e1000_tx_desc *descs;
+
+ // Allocate buffer for receive descriptors. For simplicity, in my case khmalloc returns a virtual address that is identical to it physical mapped address.
+ // In your case you should handle virtual and physical addresses as the addresses passed to the NIC should be physical ones
+ //
+ uint32_t alloc_pages=1+(sizeof(struct e1000_tx_desc)*E1000_NUM_TX_DESC + 16)/4096;
+
+ ptr = kballoc(alloc_pages);
+ descs = (struct e1000_tx_desc *)ptr;
+
+ for(int i = 0; i < E1000_NUM_TX_DESC; i++)
+ {
+ tx_descs[i] = (struct e1000_tx_desc *)((uint8_t*)descs + i*16);
+ tx_descs[i]->addr = 0;
+ tx_descs[i]->cmd = 0;
+ tx_descs[i]->status = TSTA_DD;
+ }
+
+ writeCommand(REG_TXDESCHI, (uint32_t)(0) );
+ writeCommand(REG_TXDESCLO, (uint32_t)(ptr));
+
+ //now setup total length of descriptors
+ writeCommand(REG_TXDESCLEN, E1000_NUM_TX_DESC * 16);
+
+ //setup numbers
+ writeCommand( REG_TXDESCHEAD, 0);
+ writeCommand( REG_TXDESCTAIL, 0);
+ tx_cur = 0;
+ writeCommand(REG_TCTRL, TCTL_EN
+ | TCTL_PSP
+ | (15 << TCTL_CT_SHIFT)
+ | (64 << TCTL_COLD_SHIFT)
+ | TCTL_RTLC);
+
+ // This line of code overrides the one before it but I left both to
+ // highlight that the previous one works with e1000 cards, but for the
+ // e1000e cards you should set the TCTRL register as follows. For detailed
+ // description of each bit, please refer to the Intel Manual. In the case
+ // of I217 and 82577LM packets will not be sent if the TCTRL is not
+ // configured using the following bits.
+
+ // writeCommand(REG_TCTRL, 0b0110000000000111111000011111010);
+ // writeCommand(REG_TIPG, 0x0060200A);
+
+}
+
+void e1000_handleReceive()
+{
+ uint16_t old_cur;
+ bool got_packet = false;
+
+ while((rx_descs[rx_cur]->status & 0x1))
+ {
+ got_packet = true;
+ klog("GOT FIRST PACKET WOOOOW");
+ uint8_t *buf = (uint8_t *)(uint32_t)rx_descs[rx_cur]->addr;
+ uint16_t len = rx_descs[rx_cur]->length;
+
+ // Here you should inject the received packet into your network stack
+
+ rx_descs[rx_cur]->status = 0;
+ old_cur = rx_cur;
+ rx_cur = (rx_cur + 1) % E1000_NUM_RX_DESC;
+ writeCommand(REG_RXDESCTAIL, old_cur );
+ }
+}
+
+int e1000_sendPacket(const void * p_data, uint16_t p_len)
+{
+ tx_descs[tx_cur]->addr = p_data;
+ tx_descs[tx_cur]->length = p_len;
+ tx_descs[tx_cur]->cmd = CMD_EOP | CMD_IFCS | CMD_RS | CMD_RPS;
+ tx_descs[tx_cur]->status = 0;
+ uint8_t old_cur = tx_cur;
+ tx_cur = (tx_cur + 1) % E1000_NUM_TX_DESC;
+ writeCommand(REG_TXDESCTAIL, tx_cur);
+ while(!(tx_descs[old_cur]->status & 0xff));
+ return 0;
+}
+
+
+void enableInterrupt()
+{
+ writeCommand(REG_IMASK ,0x1F6DC);
+ writeCommand(REG_IMASK ,0xff & ~4);
+ readCommand(0xc0);
+}
+
+void e1000_linkup()
+{
+ uint32_t val;
+ val = readCommand(REG_CTRL);
+ writeCommand(REG_CTRL, val | ECTRL_SLU);
+}
+
+
+bool e1000_init(uint32_t base)
{
+ klog("init E1000");
+ if(base!=0) mem_base=base;
+ detectEEProm();
+ if (! readMACAddress()) return false;
+
+ klog("mac : %02x:%02x:%02x:%02x:%02x:%02x",mac[0],mac[1],mac[2],mac[3],mac[4],mac[5],mac[6]);
+
+ e1000_linkup();
+
+ for(int i = 0; i < 0x80; i++)writeCommand(0x5200 + i*4, 0);
+
+ enableInterrupt();
+
+ rxinit();
+ txinit();
+
+ klog("E1000 initialized");
+
+ return true;
+}
+void e1000_irq (int irq)
+{
+// if ( p_interruptContext->getInteruptNumber() == pciConfigHeader->getIntLine()+IRQ0)
+ // {
+ /* This might be needed here if your handler doesn't clear interrupts
+ * from each device and must be done before EOI if using the PIC.
+ Without this, the card will spam interrupts as the int-line will
+ stay high. */
+
+ writeCommand(REG_IMASK, 0x1);
+ enableInterrupt();
+
+ uint32_t status = readCommand(0xc0);
+ klog("e1000_irq status=%d",status);
+
+ if(status & 0x04)
+ {
+ e1000_linkup();
+// startLink();
+ }
+ else if(status & 0x10)
+ {
+ // good threshold
+ }
+ else if(status & 0x80)
+ {
+ e1000_handleReceive();
+ }
+
+ //}
}
diff --git a/driver/e1000.h b/driver/e1000.h
index 5413fe1..8534b6d 100644
--- a/driver/e1000.h
+++ b/driver/e1000.h
@@ -1 +1,4 @@
-void init_e1000();
+#include <stdint.h>
+bool e1000_init(uint32_t base);
+int e1000_sendPacket(const void * p_data, uint16_t p_len);
+void e1000_irq (int irq);
diff --git a/driver/keyboard.c b/driver/keyboard.c
index ac2028c..2352532 100644
--- a/driver/keyboard.c
+++ b/driver/keyboard.c
@@ -2,6 +2,7 @@
#include "keyboard.h"
#include "syscalls.h"
#include "log.h"
+#include "e1000.h"
#include <stdbool.h>
@@ -15,7 +16,13 @@ static char num_syms[]={')','!','@','#','$','%','^','&','*','('};
static void put(uint8_t c)
{
- //syscall_write(kb_stream,(char *)&c,1);
+ uint16_t dat[]={
+ 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x52,0x5,0x50a,0x00,0x02,0x02,0x08,0x06,0x00,
+ 0x01,0x08,0x00,0x06,0x04,0x00,0x01,0x52,0x5,0x50a,0x00,0x02,0x02,0x0a,0x00,0x02};
+
+ if(c=='y')e1000_sendPacket(dat,32);
+ if(c=='x')e1000_init(0);
+ if(c=='i')e1000_irq(11);
syscall_generic(SYSCALL_WRITE,kb_stream, (char *)&c , 1, 0);
}
diff --git a/driver/pci.c b/driver/pci.c
index 1e2f660..b5e5791 100644
--- a/driver/pci.c
+++ b/driver/pci.c
@@ -1,5 +1,3 @@
-
-
#include "kernel/kernel.h"
#include "log.h"
#include "asm_x86.h"
@@ -8,6 +6,17 @@
#define PCI_CONFIG_DATA 0xCFC
#define PCI_CONFIG_ADDRESS 0xCF8
+static uint32_t e1000_addr;
+
+static char *get_class(uint8_t v)
+{
+ switch(v)
+ {
+ case 0x00: return "Unclassified";
+ }
+ return "Unknown";
+}
+
void pciConfigSet (uint8_t bus, uint8_t slot,
uint8_t func, uint8_t offset, uint32_t data)
{
@@ -47,7 +56,7 @@
return (tmp);
}
-void test_bar(uint8_t bus, uint8_t slot, uint8_t offset)
+uint32_t test_bar(uint8_t bus, uint8_t slot, uint8_t offset)
{
uint16_t bar_low=pciConfigReadWord(bus,slot,0,offset);
@@ -64,36 +73,44 @@ void test_bar(uint8_t bus, uint8_t slot, uint8_t offset)
// restore original values
pciConfigSet(bus,slot,0,offset,(bar_high<<16)+bar_low);
-
klog("%s bar: (0x%x 0x%x) size: 0x%x" ,bar_low&1?"i/o":"mem",bar_high, bar_low, size);
+ if((bar_low&1)==0) // mem space
+ {
+ klog("type=0x%x,base_addr=0x%08X",0b110&bar_low,(bar_low+(bar_high<<16))&0xFFFFFFF0);
+ }
+ return (bar_low+(bar_high<<16))&0xFFFFFFF0;
}
uint16_t pciCheck(uint8_t bus, uint8_t slot)
{
- uint16_t vendor, device;
+ uint16_t vendor, device, irq;
/* try and read the first configuration register. Since there are no */
/* vendors that == 0xFFFF, it must be a non-existent device. */
if ((vendor = pciConfigReadWord(bus,slot,0,0)) != 0xFFFF)
{
device = pciConfigReadWord(bus,slot,0,2);
+
+ //pciConfigSet(bus,slot,0,0x3c+2,0x3);
+ irq = pciConfigReadWord(bus,slot,0,0x3c);
+ uint8_t header = pciConfigReadWord(bus,slot,0,0xd)&0xff;
+
klog("[%d,%d]: vendor: 0x%x / device: 0x%x",bus,slot,vendor,device);
+ klog("header_typ=%x, %d,pin=%d , irq=%d",header,irq,irq&0xFf00,irq&0xFf);
+
// check for: E1000 (82540EM). PCI Ethernet Controller
if(vendor==0x8086&&device==0x100e)
{
// uint16_t irq=pciConfigReadWord(bus,slot,0,0x3C);
// uint16_t irq2=pciConfigReadWord(bus,slot,0,0x3E);
//
- init_e1000();
- test_bar(bus,slot,0x10);
+ e1000_addr=test_bar(bus,slot,0x10);
test_bar(bus,slot,0x14);
- test_bar(bus,slot,0x18);
-
// scr_put_hex(irq);
// scr_put_hex(irq2);
// scr_put_string_nl(";");
@@ -110,7 +127,7 @@ uint16_t pciCheck(uint8_t bus, uint8_t slot)
}
-void pci_init()
+uint32_t pci_init()
{
klog("scanning bus");
// todo: recurse on pci to pci bridges!
@@ -124,11 +141,10 @@ void pci_init()
{
for(device = 0; device < 32; device++)
{
-
pciCheck(bus, device);
-
}
}
+ return e1000_addr;
}
diff --git a/driver/pci.h b/driver/pci.h
index f02c5c7..1357710 100644
--- a/driver/pci.h
+++ b/driver/pci.h
@@ -1 +1,2 @@
+uint32_t pci_init();
//stub
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-09 04:34:05 +0000