1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
|
#include "kernel.h"
enum PAGE_PTE_FLAGS {
I86_PTE_PRESENT = 1, //0000000000000000000000000000001
I86_PTE_WRITABLE = 2, //0000000000000000000000000000010
I86_PTE_USER = 4, //0000000000000000000000000000100
I86_PTE_WRITETHOUGH = 8, //0000000000000000000000000001000
I86_PTE_NOT_CACHEABLE = 0x10, //0000000000000000000000000010000
I86_PTE_ACCESSED = 0x20, //0000000000000000000000000100000
I86_PTE_DIRTY = 0x40, //0000000000000000000000001000000
I86_PTE_PAT = 0x80, //0000000000000000000000010000000
I86_PTE_CPU_GLOBAL = 0x100, //0000000000000000000000100000000
I86_PTE_LV4_GLOBAL = 0x200, //0000000000000000000001000000000
I86_PTE_FRAME = 0x7FFFF000 //1111111111111111111000000000000
};
enum PAGE_PDE_FLAGS {
I86_PDE_PRESENT = 1, //0000000000000000000000000000001
I86_PDE_WRITABLE = 2, //0000000000000000000000000000010
I86_PDE_USER = 4, //0000000000000000000000000000100
I86_PDE_PWT = 8, //0000000000000000000000000001000
I86_PDE_PCD = 0x10, //0000000000000000000000000010000
I86_PDE_ACCESSED = 0x20, //0000000000000000000000000100000
I86_PDE_DIRTY = 0x40, //0000000000000000000000001000000
I86_PDE_4MB = 0x80, //0000000000000000000000010000000
I86_PDE_CPU_GLOBAL = 0x100, //0000000000000000000000100000000
I86_PDE_LV4_GLOBAL = 0x200, //0000000000000000000001000000000
I86_PDE_FRAME = 0x7FFFF000 //1111111111111111111000000000000
};
//! page table entry
typedef uint32_t pt_entry;
//! a page directery entry
typedef uint32_t pd_entry;
////
//! virtual address
typedef uint32_t virtual_addr;
typedef uint32_t physical_addr;
typedef uint8_t bool;
//! i86 architecture defines 1024 entries per table--do not change
#define PAGES_PER_TABLE 1024
#define PAGES_PER_DIR 1024
#define PAGE_DIRECTORY_INDEX(x) (((x) >> 22) & 0x3ff)
#define PAGE_TABLE_INDEX(x) (((x) >> 12) & 0x3ff)
#define PAGE_GET_PHYSICAL_ADDRESS(x) (*x & ~0xfff)
//! page table represents 4mb address space
#define PTABLE_ADDR_SPACE_SIZE 0x400000
//! directory table represents 4gb address space
#define DTABLE_ADDR_SPACE_SIZE 0x100000000
//! page sizes are 4k
#define PAGE_SIZE 4096
//! page table
struct ptable {
pt_entry m_entries[PAGES_PER_TABLE];
};
//! page directory
struct pdirectory {
pd_entry m_entries[PAGES_PER_DIR];
};
void pt_entry_add_attrib (pt_entry* e, uint32_t attrib)
{
}
void pt_entry_del_attrib (pt_entry* e, uint32_t attrib)
{
}
void pt_entry_set_frame (pt_entry* e , physical_addr addr)
{
}
bool pt_entry_is_present (pt_entry e)
{
return 1;
}
bool pt_entry_is_writable (pt_entry e)
{
return 1;
}
physical_addr pt_entry_pfn (pt_entry e)
{
return 1;
}
void pd_entry_add_attrib (pd_entry* e, uint32_t attrib)
{
}
void pd_entry_del_attrib (pd_entry* e, uint32_t attrib)
{
}
void pd_entry_set_frame (pd_entry* e, physical_addr add)
{
}
bool pd_entry_is_present (pd_entry e)
{
return 1;
}
bool pd_entry_is_user (pd_entry e)
{
return 1;
}
bool pd_entry_is_4mb (pd_entry e)
{
return 1;
}
bool pd_entry_is_writable (pd_entry e)
{
return 1;
}
physical_addr pd_entry_pfn (pd_entry e)
{
return 1;
}
void pd_entry_enable_global (pd_entry e)
{
}
uint8_t vmmngr_alloc_page (pt_entry* e)
{
//! allocate a free physical frame
void* p = pmmngr_alloc_block ();
if (!p)
return 0;
//! map it to the page
pt_entry_set_frame (e, (physical_addr)p);
pt_entry_add_attrib (e, I86_PTE_PRESENT);
return 1;
}
void vmem_init()
{
scr_put_string_nl("vmem: Init paging\nxxx");
int x=10/0;
}
|
